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e product preview ma y 1998 order number: 290644-001 n high performance ? 54 mhz effective zero wait-state performance ? synchronous burst-mode reads ? asynchronous page-mode reads n smartvoltage technology ? 2.7 v - 3.6 v read and write operations for low power designs ? 12 v v pp fast factory programming n flexible i/o voltage ? 1.65 v i/o reduces overall system power consumption ? 5 v-safe i/o enables interfacing to 5 v devices n enhanced data protection ? absolute write protection with v pp = gnd ? block locking ? block erase/program lockout during power transitions n density upgrade path ? 8- and 16-mbit n manufactured on etox? v flash technology n supports code plus data storage ? optimized for flash data integrator (fdi) software ? fast program suspend capability ? fast erase suspend capability n flexible blocking architecture ? eight 4-kword blocks for data ? 32-kword main blocks for code ? top or bottom configurations available n extended cycling capability ? minimum 10,000 block erase cycles guaranteed n low power consumption ? automatic power savings mode decreases power consumption n automated program and block erase algorithms ? command user interface for automation ? status register for system feedback n industry-standard packaging ? 56-lead ssop ? m bga* csp intels fast boot block memory family renders high performance asynchronous page-mode and synchronous burst reads making it an ideal memory solution for burst cpus. combining high read performance with the intrinsic non-volatility of flash memory, this flash memory family eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory for improved system performance. therefore, it r educes the total memory requirement which helps increase reliability and reduce overall system power consumption and cost. this family of products is manufactured on intels 0.4 m m etox? v process technology. they are available in industry-standard packages: the m bga* csp, ideal for board-constrained applications, and the rugged 56-lead ssop. fast boot block flash memory family 8 and 16 mbit 28f800f3, 28f160f3 includes extended and automotive temperature specifications
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f800f3, 28f160f3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation, 1998 cg-041493 *third-part y brands and names are the propert y of their respective owners
e fast boot block datasheet 3 product preview contents page page 1.0 introduction .............................................5 1.2 product overview.........................................5 2.0 product description..............................6 2.1 pinouts.........................................................6 2.2 pin description.............................................6 2.3 memory blocking organization.....................9 2.3.1 parameter blocks ..................................9 2.3.2 main blocks ...........................................9 3.0 principles of operation .....................12 3.1 bus operations ..........................................12 3.1.1 read....................................................12 3.1.2 output disable.....................................12 3.1.3 standby ...............................................12 3.1.4 write....................................................12 3.1.5 reset...................................................13 4.0 command definitions ............................13 4.1 read array command................................15 4.2 read identifier codes command ...............15 4.3 read status register command................15 4.4 clear status register command................15 4.5 block erase command ..............................15 4.6 program command....................................17 4.7 block erase suspend/resume command .17 4.8 program suspend/resume command.......17 4.9 set read configuration command.............19 4.9.1 read configuration..............................19 4.9.2 frequency configuration .....................20 4.9.3 data output configuration ...................20 4.9.4 wait# configuration ...........................20 4.9.5 burst sequence...................................20 4.9.6 clock configuration .............................20 4.9.7 burst length ........................................20 5.0 data protection.....................................26 5.1 v pp = v il for complete protection ..............26 5.2 wp# = v il for block locking ......................26 5.3 wp# = v ih for block unlocking...................26 6.0 v pp voltages ............................................26 7.0 power consumption..............................26 7.1 active power ..............................................26 7.2 automatic power savings ..........................26 7.3 standby power...........................................27 7.4 power-up/down operation.........................27 7.4.1 rst# connection ................................27 7.4.2 v cc , v pp and rst# transitions ...........27 7.5 power supply decoupling ..........................27 7.5.1 v pp trace on printed circuit boards ....27 8.0 electrical specifications .................28 8.1 absolute maximum ratings........................28 8.2 extended temperature operating conditions .................................................28 8.3 capacitance ...............................................29 8.4 dc characteristics extended temperature..............................................30 8.5 ac characteristicsread-only operations extended temperature .........32 8.6 ac characteristicswrite operations extended temperature..............................38 8.7 ac characteristicsreset operation extended temperature..............................40 8.8 extended temperature block erase and program performance ...............................41 8.9 automotive temperature operating conditions .................................................41
fast boot block datasheet e 4 product preview 8.10 capacitance .............................................42 8.11 dc characteristics automotive temperature..............................................43 8.12 ac characteristicsread-only operationsautomotive temperature ......44 8.13 automotive temperature frequency configuration settings ...............................45 8.14 automotive temperature block erase and program performance ...............................45 9.0 ordering information..........................46 10.0 additional information .....................47 revision history date of revision version description 05/12/98 -001 original version
e fast boot block datasheet 5 product preview 1.0 introduction this datasheet contains 8- and 16-mbit fast boot block memory information. section 1.0 provides a flash memory overview. sections 2.0 through 8.0 describe the memory functionality and electrical specifications for extended and automotive temperature product offerings. 1.2 product overview the fast boot block flash memory family provides density upgrades with pinout compatibility for 8- and 16-mbit densities. this family of products are high performance, low voltage memories with a 16-bit data bus and individually erasable blo cks. these blocks are optimally sized for c ode and data storage. eight 4-kword parameter blo cks are positioned at either the top (denoted by -t suffix) or bottom (denoted by -b suffix) of the address map. the rest of the device is grouped into 32-kword main blocks. the upper two (or lower two) parameter and all main blo cks can be locked for complete code protection. the devices optimized architecture and interface dramatically increases read performance beyond previously attainable levels. it supports asynchronous page-mode and synchronous burst reads from main blo cks (parameter blocks s upport single asynchronous and synchronous reads). upon initial power-up or return from reset, the device defaults to a page-mode read configuration. page-mode read configuration is ideal for non-clock memory systems and is compatible with page- mode rom. synchronous burst reads are enabled by writing to the read configuration register. in synchronous burst mode, the clk input increments an internal burst address generator, synchronizes the flash memory with the host cpu, and outputs data on every rising (or falling) clk edge up to 54 mhz (25 mhz for automotive temperature). an output signal, wait#, is also provided to ease cpu to flash memory communication and synchronization during continuous burst operations. in addition to the enhanced architecture and interface, this family of products incorporates smartvoltage technology which enables fast factory programming and low power designs. specifically designed for low voltage systems, fast boot block flash memory components support read operations at 2.7 v (3.3 v for automotive temperature) v cc and block erase and program operations at 2.7 v (3.3 v for automotive temperature) and 12 v v pp . the 12 v v pp option renders the fastest program performance to increase factory programming throughput. with the 2.7 v (3.3 v for automotive temperature) v pp option, v cc and v pp can be tied together for a simple, low power design. in addition to the voltage flexibility, the dedicated v pp pin gives complete data protection when v pp v pplk . the flexible input/output (i/o) voltage capability helps reduce system power consumption and simplify interfacing to sub 2.7 v and 5 v cpus. powered by v ccq pins, the i/o buffers can operate at a lower voltage than the flash memory core. with v ccq voltage at 1.65 v, the i/os swing between gnd and 1.65 v, reducing i/o power consumption by 65% over standard 3 v flash memory components. the low voltage and 5 v-safe feature also helps ease cpu interfacing by adapting to the cpus bus voltage. the devices command user interface (cui) serves as the interface between the system processor and internal flash memory operation. a valid command sequence written to the cui initiates device automation. this automation is controlled by an internal write state machine (wsm) which automatically executes the algorithms and timings necessary for block erase and program operations. the status register provides wsm feedback by signifying block erase or program completion and status. block erase and program automation allows erase and program operations to be executed using an industry-standard two-write command sequence. a block erase operation erases one block at a time, and data is programmed in word increments. erase suspend allows system software to sus pend an ongoing block erase operation in order to read from or program data to any other block. program suspend allows system software to sus pend an ongoing program operation in order to read from any other location. fast boot block flash memory devices offer two low power savings features: automatic power savings (aps) and standby mode. the device automatically enters aps mode following the completion of a read cycle. st andby mode is initiated when the system deselects the device by driving ce# inactive or rst# active. rst# also resets the device to read array, provides write protection, and clears the status register. combined, these two features significantly reduce power consumption.
fast boot block datasheet e 6 product preview 2.0 product description this section describes the pinout and block architecture of the device family. 2.1 pinouts intels fast boot block flash memory family provides upgrade paths in each package pinout up to the 16-mbit density. the family is available in m bga csp and 56-lead ssop packages. pinouts for the 8- and 16-mbit components are illustrated in figures 1 and 2. 2.2 pin description the pin description table describes pin usage. 123456789 a b c d e f 10 a 14 a 15 a 12 a 11 a 8 gnd a 20 we# clk v cc a 19 v pp a 17 a 5 a 4 a 13 a 10 a 21 a 18 a 7 a 6 a 1 a 2 a 3 a 9 wp# rst# adv# v ccq dq 7 dq 12 dq 10 dq 9 dq 0 ce# dq 13 dq 11 dq 4 a 16 dq 15 dq 6 dq 2 dq 1 oe# wait# gnd dq 14 gnd v ccq dq 8 gnd a 0 dq 5 dq 3 v cc 16m 32m 64m notes: 1. shaded connections indicate upgrade address connections. lower density devices will not have upper address solder balls. routing is not recommended in this area. 2. a 20 and a 21 are the upgrade address for potential 32-mbit and 64-mbit devices (currently not on road map). 3. reference the micro ball grid array package mechanical specification and media information on intels world wide web home page for detailed package specifications. figure 1. 56-ball bga* package pinout (top view, ball down)
e fast boot block datasheet 7 product preview 16-mbit we# we# rst# rst# v pp v pp wp# wp# nc a 19 a 1 a 1 a 2 a 2 a 3 a 3 a 4 a 4 a 5 a 5 a 6 a 6 a 7 a 7 a 17 a 17 a 18 a 18 dq 9 dq 9 dq 1 dq 1 dq 8 dq 8 dq 0 dq 0 oe# oe# gnd gnd ce# ce# a 0 a 0 nc nc v ccq v ccq dq 2 dq 2 dq 10 dq 10 dq 3 dq 3 dq 11 dq 11 v cc v cc clk clk adv# adv# gnd gnd nc nc a 15 a 15 a 14 a 14 a 13 a 13 a 12 a 12 a 11 a 11 a 10 a 10 a 9 a 9 a 8 a 8 nc nc gnd gnd dq 6 dq 6 dq 14 dq 14 dq 7 dq 7 dq 15 dq 15 gnd gnd v ccq v ccq a 16 a 16 wait# wait# dq 13 dq 13 dq 5 dq 5 dq 12 dq 12 dq 4 dq 4 v cc v cc 56-lead ssop 16 mm x 23.7 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 8-mbit 8-mbit 16-mbit figure 2. ssop pinout
fast boot block datasheet e 8 product preview table 1. pin descriptions sym type name and function a 0 Ca 19 input address inputs: inputs for addresses during read and write operations. addresses are internally latched during read and write cycles. 8-mbit: a 0 C18 , 16-mbit: a 0C19 dq 0 C dq 15 input/ output data input/outputs: inputs data and commands during write cycles, outputs data during memory array, status register (dq 0 Cdq 7 ), and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. clk input clock: synchronizes the flash memory to the system operating frequency during synchronous burst-mode read operations. when configured for synchronous burst- mode reads, address is latched on the first rising (or falling, depending upon the read configuration register setting) clk edge when adv# is active or upon a rising adv# edge, whichever occurs first. clk is ignored during asynchronous page- mode read and write operations. adv# input address valid: indicates that a valid address is present on the address inputs. addresses are latched on the rising edge of adv# during read and write operations. adv# may be tied active during asynchronous read and write operations. ce# input chip enable: activates the devices control logic, input buffers, decoders, and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. rst# input reset: when driven low, rst# inhibits write operations which provides data protection during power transitions, and it resets internal automation. rst#-high enables normal operation. exit from reset sets the device to asynchronous read array mode. oe# input output enable: gates data outputs during a read cycle. we# input write enable: controls writes to the cui and array. addresses and data are latched on the rising edge of the we# pulse. wp# input write protection: provides a method for locking and unlocking all main blocks and two parameter blocks. when wp# is at logic low, lockable blocks are locked. if a program or erase operation is attempted on a locked block, sr.1 and either sr.4 [program] or sr.5 [block erase] will be set to indicate the operation failed. when wp# is at logic high, the lockable blocks are unlocked and can be programmed or erased. wait# output wait: provides data valid feedback when configured for synchronous burst-mode and the burst length is set to continuous. this signal is gated by oe# and ce# and is internally pull-up to v ccq via a resistor. wait# from several components can be tied together to form one system wait# signal.
e fast boot block datasheet 9 product preview table 1. pin descriptions sym type name and function v pp supply block erase and program power supply (2.7 v C3.6 v, 11.4 vC12.6 v): for erasing array blocks or programming data, a valid voltage must be applied to this pin. with v pp v ppl k , memory contents cannot be altered. block erase and program with an invalid v pp voltage should not be attempted. applying 11.4 v C12.6 v to v pp can only be done for a maximum of 1000 cycles on main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum (see section 6.0 for details). v cc supply device power supply (2.7 v C3.6 v): with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltages should not be attempted. v ccq supply output power supply (1.65 vC2.5 v, 2.7 vC3.6 v): enables all outputs to be driven to 1.65 v to 2.5 v or 2.7 v to 3.6 v. when v ccq equals 1.65 v C2.5 v, v cc voltage must not exceed 3.3 v and should be regulated to 2.7 vC2.85 v to achieve lowest power operation (see dc characteristics for detailed information). this input may be tied directly to v cc . gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated. 2.3 memory blocking organization the fast boot block flash memory family is an asymmetrically-blocked architecture that enables system integration of c ode and data within a single flash device. for the address locations of each block, see the memory maps in figure 3 (top boot blocking) and figure 4 (bottom boot blocking). 2.3.1 parameter blocks the fast boot block flash memory architecture includes parameter blo cks to facilitate stor age of frequently updated small parameters that would normally be stored in an eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. each 8- and 16-mbit device contains eight 4-kwords (4,096-words) parameter blocks. 2.3.2 main blocks after the parameter blocks, the remai nder of the array is divided into equal size main blo cks for code and/or data storage. the 8-mbit device contains fifteen 32-kword (32,768-word) main blo cks, and the 16-mbit device contains thirty-one 32-kword (32,768-word) main blocks.
fast boot block datasheet e 10 product preview 32-kword 32-kword 32-kword address range 78000h - 78fffh 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 10000h - 17fffh 08000h - 0ffffh 00000h - 07fffh 8-mbit 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword block 22 block 21 block 20 block 19 block 18 block 17 block 16 block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 79000h - 79fffh 7a000h - 7afffh 7b000h - 7bfffh 7c000h - 7cfffh 7d000h - 7dfffh 7e000h - 7efffh 7f000h - 7ffffh 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 32-kword 32-kword 32-kword address range f8000h - f8fffh f0000h - f7fffh e8000h - effffh e0000h - e7fffh d8000h - dffffh d0000h - d7fffh c8000h - cffffh c0000h - c7fffh b8000h - bffffh b0000h - b7fffh a8000h - affffh a0000h - a7fffh 98000h - 9ffffh 90000h - 97fffh 88000h - 8ffffh 80000h - 87fffh 16-mbit 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword block 38 block 37 block 36 block 35 block 34 block 33 block 32 block 31 block 30 block 29 block 28 block 27 block 26 block 25 block 24 block 23 block 22 block 21 block 20 block 19 block 18 block 17 block 16 f9000h - f9fffh fa000h - fafffh fb000h - fbfffh fc000h - fcfffh fd000h - fdfffh fe000h - fefffh ff000h - fffffh 32-kword 32-kword 78000h - 7ffffh 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 10000h - 17fffh 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 block 2 08000h - 0ffffh 00000h - 07fffh 32-kword 32-kword block 1 block 0 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword figure 3. 8- and 16-mbit top boot memory map
e fast boot block datasheet 11 product preview address range 16-mbit 32-kword 32-kword 32-kword f8000h - fffffh f0000h - f7fffh e8000h - effffh e0000h - e7fffh d8000h - dffffh d0000h - d7fffh c8000h - cffffh c0000h - c7fffh b8000h - bffffh b0000h - b7fffh a8000h - affffh a0000h - a7fffh 98000h - 9ffffh 90000h - 97fffh 88000h - 8ffffh 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword block 38 block 37 block 36 block 35 block 34 block 33 block 32 block 31 block 30 block 29 block 28 block 27 block 26 block 25 block 24 32-kword 32-kword 80000h - 87fffh 78000h - 7ffffh 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword block 23 block 22 block 21 block 20 block 19 block 18 block 17 block 16 block 15 block 14 block 13 block 12 block 11 block 10 10000h - 17fffh 32-kword block 9 00000h - 00fffh block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 01000h - 01fffh 02000h - 02fffh 03000h - 03fffh 04000h - 04fffh 05000h - 05fffh 06000h - 06fffh 07000h - 07fffh 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 32-kword block 8 08000h - 0ffffh 32-kword 32-kword 32-kword address range 78000h - 7ffffh 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 10000h - 17fffh 08000h - 0ffffh 8-mbit 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword 32-kword block 22 block 21 block 20 block 19 block 18 block 17 block 16 block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 00000h - 00fffh 01000h - 01fffh 02000h - 02fffh 03000h - 03fffh 04000h - 04fffh 05000h - 05fffh 06000h - 06fffh 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 4-kword 07000h - 07fffh figure 4. 8- and 16-mbit bottom boot memory map
fast boot block datasheet e 12 product preview 3.0 principles of operation the fast boot block flash memory components include an on-chip wsm to manage block erase and program. it allows for cmos-level control inputs, fixed power supplies, and minimal processor overhead with ram-like interface timings. 3.1 bus operations all bus cycles to and from flash memory conform to standard microprocessor bus cycles. 3.1.1 read the flash memory has three read modes available: read array, identifier codes, and status register. these modes are accessible independent of the v pp voltage. the appropriate read command (read array, read identifier codes, or read status register) must be written to the cui to enter the requested read mode. upon initial power-up or exit from reset, the device defaults to read array mode. when reading information from main blo cks in read array mode, the device supports two high- performance read configurations: asynchronous page-mode and synchronous burst-mode. asynchronous page-mode is the default state and provides high data transfer rate for non-clocked memory subsystems. in this state, data is internally read and stored in a high-speed page buffer. a 1:0 addresses data in the page buffer. the page size is four words. the other read configuration, synchronous burst-mode, is enabled by writing to read configuration register. this register sets the read configuration, burst order, frequency configuration, and burst length. in synchronous burst-mode, the device latches the initial address then outputs a sequence of data with respect to the input clk and read configuration setting. read operations from the parameter blo cks, identifier codes and status register transpire as single asynchronous or synchronous read cycles. the read configuration register setting determines whether or not read operations are asynchronous or synchronous. for all read operations, ce# must be driven active to enable the devices, adv# must be driven low to open the internal address latch, and oe# must be driven low to activate the outputs. in asynchronous mode, the address is latched when adv# is driven high. in synchronous mode, the address is latched by adv# going high or adv# low in conjunction with a rising (falling) clock edge, whichever occurs first. we# must be at v ih . figures 14 through 19 illustrate different read cycles. 3.1.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 Cdq 15 are placed in a high-impedance state. 3.1.3 standby deselecting the device by bringing ce# to a logic- high level (v ih ) places the device in standby mode, which substantially reduces device power consumption. in standby, outputs are placed in a high-impedance state independent of oe#. if deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 write commands are written to the cui using standard microprocessor write timings when adv#, we#, and ce# are active and oe# inactive. the cui does not occupy an addressable memory location. the address is latched on the rising edge of adv#, we#, or ce# (whichever occurs first) and data needed to execute a command is latched on the rising edge of we# or ce# (whichever goes high first). write operations are asynchronous. therefore, clk is ignored during write operations. figure 20 illustrates a write operation.
e fast boot block datasheet 13 product preview 3.1.5 reset the device enters a reset mode when rst# is driven low. in reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. after return from reset, a time t phqv is required until outputs are valid, and a delay (t phwl or t phel ) is required before a write sequence can be initiated. after this wake-up interval, normal operation is restored. the device defaults to read array mode, the status register is set to 80h, and the read configuration register defaults to asynchronous page-mode reads. if rp# is taken low during a block erase or program operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. see figure 21 for detailed information regarding reset timings. 4.0 command definitions device operations are selected by writing specific commands into the cui. table 3 defines these commands. table 2. bus operations mode notes rst# ce# adv# oe# we# address v pp dq 0 C15 reset v il xxxxxx high z standby v ih v ih xxxxx high z output disable v ih v il xv ih v ih x x high z read 1,2 v ih v il v il v il v ih xxd out read identifier codes v ih v il v il v il v ih see table 4 x see table 4 write 3,4 v ih v il v il v ih v il xx d in notes: 1. refer to dc characteristics . when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control and address input pins and v pplk or v pph1/2 for v pp . see dc characteristics for v pplk and v pph1/2 voltages. 3. command writes involving block erase or program are reliably executed when v pp = v pph1/2 and v cc = v cc1/2 (see section 8 for operating conditions at different temperatures). 4. refer to table 3 for valid d in during a write operation.
fast boot block datasheet e 14 product preview table 3. command definitions (1) bus cycles first bus cycle second bus cycle command req'd. notes oper (2) addr (3) data (4) oper (2) addr (3) data (4) read array/reset 1 write x ffh read identifier codes 3 2 5 write x 90h read ia id read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 6,7 write x 20h write ba d0h program 2 6,7,8 write x 40h or 10h write wa wd block erase and program suspend 1 6 write x b0h block erase and program resume 1 6 write x d0h set read configuration 2 write x 60h write rcd 03h notes: 1. commands other than those shown above are reserved by intel for future device implementations and should not be used. 2. bus operations are defined in table 2. 3. x = any valid address within the device. ia = identifier code address. ba = address within the block being erased. wa = address of memory location to be written. rcd = data to be written to the read configuration register. this data is presented to the device on a 15-0 ; set all other address inputs to 0. 4. srd = data read from status register. see table 5 for a description of the status register bits. wd = data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id = data read from identifier codes. see table 4 for manufacturer and device codes. rcd = data to be written to read configuration register. see table 6 for a description of the read configuration register bits. 5. following the read identifier codes command, read operations access manufacturer, device codes, and read configuration register. 6. following a block erase, program, and suspend operation, read operations access the status register. 7. to issue a block erase, program, or suspend operation to a lockable block, hold wp# at v ih . 8. either 40h or 10h are recognized by the wsm as the program setup.
e fast boot block datasheet 15 product preview 4.1 read array command upon initial device power-up or exit from reset, the device defaults to read array mode. the read configuration register defaults to asynchronous page-mode. the read array command also causes the device to enter read array mode. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase or program, the device will not recognize the read array command until the wsm completes its operation or unless the wsm is suspended via an erase or program suspend command. the read array command functions independently of the v pp voltage. 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. after writing the command, read cycles retrieve the manufacturer and device codes (see table 4 for identifier code values). page-mode and burst reads are not supported in this read mode. to terminate the operation, write another valid command, like the read array command. the read identifier codes command functions independently of the v pp voltage. table 4. identifier codes code address (hex) data (hex) manufacturer code 00000 0089 device code 8 mbit -t 00001 88f1 -b 00001 88f2 16 mbit -t 00001 88f3 -b 00001 88f4 4.3 read status register command the status register can be read at any time by writing the read status register command to the cui. after writing this command, all subsequent read operations output status register data until another valid command is written. page-mode and burst reads are not supported in this read mode. the status register content is updated and latched on the rising edge of adv# or rising (falling) clk edge when adv# is low during synchronous burst- mode or the falling edge of oe# or ce#, whichever occurs first. the read status register command functions independently of the v pp voltage. 4.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to 1s by the wsm and can only be cleared by issuing the clear status register command. these bits indicate various error conditions. by allowing system software to reset these bits, several operations may be performed (such as cumulatively erasing or writing several bytes in sequence). the status register may be polled to determine if a problem occurred during the sequence. the clear status register command functions independently of the applied v pp voltage. after executing this command, the device returns to read array mode. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle comm and. a block erase setup is written first, followed by a block erase confirm. this command sequence requires appropriate sequencing and address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm. after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 7, automated block erase flowchart ). the cpu can detect block erase completion by analyzing status register bit sr.7. when the block erase completes, check status register bit sr.5 for an error flag (1). if an error is detected, check status register bits sr.4, sr.3, and sr.1 to understand what caused the failure. after examining the status register, it should be cleared if an error was detected before issuing a new command. the device will remain in status register read mode until another command is written to the cui.
fast boot block datasheet e 16 product preview table 5. status register definition wsms ess es ps vpps pss dps r 76543210 notes: sr.7 = write state machine status (wsms) 1 = ready 0 = busy check sr.7 to determine block erase or program completion. sr.6 C0 are invalid while sr.7 = 0. sr.6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed when an erase suspend command is issued, the wsm halts execution and sets both sr.7 and sr.6 to 1. sr.6 remains set until an erase resume command is written to the cui. sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase if both sr.5 and sr.4 are 1s after a block erase or program attempt, an improper command sequence was entered. sr.4 = program status (ps) 1 = error in program 0 = successful program sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.3 does not provide a continuous v pp feedback. the wsm interrogates and indicates the v pp level only after a block erase or program operation. sr.3 is not guaranteed to reports accurate feedback when v pp 1 v pph1/2 or v pplk . sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when an program suspend command is issued, the wsm halts execution and sets both sr.7 and sr.2 to 1. sr.2 remains set until an program resume command is written to the cui. sr.1 = device protect status (dps) 1 = block erase or program attempted on a locked block, operation abort 0 = unlocked if a block erase or program operation is attempted to a locked block, sr.1 is set by the wsm and aborts the operation if wp# = v il . sr.0 = reserved for future enhancements (r) sr.0 is reserved for future use and should be masked out when polling the status register.
e fast boot block datasheet 17 product preview 4.6 program command program operation is executed by a two- cycle command sequence. program setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data. the wsm then takes over, controlling the internal program algorithm. after the program sequence is written, the device automatically outputs status register data when read (see figure 8, automated program flowchart ). the cpu can detect the completion of the program event by analyzing status register bit sr.7. when the program operation completes, check status register bit sr.4 for an error flag ( 1). if an error is detected, check status register bits sr.5, sr.3, and sr.1 to understand what caused the problem. after examining the status register, it should be cleared if an error was detected before issuing a new command. the device will remain in status register read mode until another command is written to the cui. 4.7 block erase suspend/resume command the block erase suspend command allows block erase interruption to read or program data in another blo cks. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase operation after a certain latency period. the device continues to output status register data when read after the block erase suspend command is issued. status register bits sr.7 and sr.6 indicate when the block erase operation has been suspended (both will be set to 1). specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blo cks other t han that which is suspended. a program command sequence can also be issued during erase suspend to program data in other blocks. using the program sus pend command (see section 4.8), a program operation can be suspended during an erase suspend. the only other valid commands while block erase is suspended are read status register and block erase resume. during a block erase suspend, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. v pp must remain at v pph1/2 while block erase is suspended. wp# must also remain at v il or v ih . to resume the block erase operation, write the block erase resume command to the cui. this will automatically clear status register bits sr.6 and sr.7. after the erase resume command is written, the device automatically outputs status register data when read (see figure 9, block erase suspend/resume flowchart ). block erase cannot resume until program operations initiated during block erase suspend have completed. 4.8 program suspend/resume command the program suspend command allows program interruption to read data in other flash memory locations. once the program process starts, writing the program suspend command requests that the wsm suspend the program operation after a certain latency period. the device continues to output status register data when read after issuing program suspend command. status register bits sr.7 and sr.2 indicate when the block erase operation has been suspended (both will be set to 1). specification t whrh1 defines the program suspend latency. at this point, a read array command can be written to read data from blo cks other t han that which is suspended. the only other valid commands while block erase is suspended are read status register and program resume. during a program suspend, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. v pp must remain at v pph1/2 while program is suspended. wp# must also remain at v il or v ih . to resume the program, write the program resume command to the cui. this will automatically clear status register bits sr.7 and sr.2. after the erase resume command is written, the device automatically outputs status register data when read (see figure 10, program suspend/resume flowchart ).
fast boot block datasheet e 18 product preview table 6. read configuration register definition rm r fc2 fc1 fc0 r doc wc 15 14 13 12 11 10 9 8 bs cc r r r bl2 bl1 bl0 7654 3 210 notes: rcr.15 = read mode (rm) 0 = synchronous burst reads enabled 1 = page-mode reads enabled (default) read mode configuration effects reads from main blocks. parameter block, status register, and identifier reads support single read cycles. rcr.14 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to 0. rcr.13 C11 = frequency configuration (fc2-0) 001 = code 1 reserved for future use 010 = code 2 011 = code 3 100 = code 4 101 = code 5 110 = code 6 see section 4.9.2 for information about the frequency configuration and its effect on the initial read. undocumented combinations of bits rcr.14 C11 are reserved by intel corporation for future implementations and should not be used. rcr.10 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to 0. rcr.9 = data output configuration (doc) 0 = hold data for one clock 1 = hold data for two clocks undocumented combinations of bits rcr.10C9 are reserved by intel corporation for future implementations and should not be used. rcr.8 = wait configuration (wc) 0 = wait# asserted during delay 1 = wait# asserted one data cycle before delay rcr.7 = burst sequence (bs) 0 = intel burst order 1 = linear burst order rcr.6 = clock configuration (cc) 0 = burst starts and data output on falling clock edge 1 = burst starts and data output on rising clock edge rcr.5C3 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to 0. rcr.2C0 = burst length (bl2C0) 001 = 4 word burst 010 = 8 word burst 111 = continuous burst in the asynchronous page mode, the burst length always equals four words. undocumented combinations of bits rcr.2C0 are reserved by intel corporation for future implementations and should not be used
e fast boot block datasheet 19 product preview adv# (v) a 19-0 (a) valid address clk (c) dq 15-0 (d/q) valid output dq 15-0 (d/q) valid output valid output valid output valid output dq 15-0 (d/q) valid output valid output valid output valid output dq 15-0 (d/q) valid output valid output dq 15-0 (d/q) valid output valid output valid output valid output code 2 code 3 code 4 code 5 code 6 figure 5. frequency configuration table 7. frequency configuration settings (1) frequency input clk frequency configuration product = -90 product = -120 code v cc = 3.0 v-3.6 v v cc = 2.7 v-3.6 v v cc = 2.7 v-3.6 v 1 reserved reserved reserved 2 27 mhz 25 mhz 20 mhz 3 40 mhz 33 mhz 28 mhz 4 54 mhz 50 mhz 40 mhz 5 66 mhz 60 mhz 50 mhz 6- 66 mhz 60 mhz notes: 1. reference section 4.1. automotive temperature frequency configuration settings for the corresponding frequency configuration codes to different input clk frequencies. 4.9 set read configuration command the set read configuration command writes data to the read configuration register. this operation is initiated by a two-cycle comm and sequence. read configuration setup is written, followed by a second write that specifies the data to be written to the read configuration register. this data is placed on the address bus, a 15:0 , and is latched on the rising edge of adv#, ce#, or we# (whichever occurs first). the read configuration data sets the devices read configuration, burst order, frequency configuration, and burst length. the command functions independently of the applied v pp voltage. after executing this command, the device returns to read array mode. 4.9.1 read configuration the device supports two high performance read configurations: asynchronous page-mode and
fast boot block datasheet e 20 product preview synchronous burst-mode. bit rcr.15 in the read configuration register sets the read configuration. asynchronous page-mode is the default read configuration state. parameter blocks, status register, and identifier only support single asynchronous and synchronous read operations. 4.9.2 frequency configuration the frequency configuration informs the device of the number of clocks that must elapse after adv# is driven active before data will be available. this value is determined by the input clock frequency. see table 7 for the specific input clk frequency configuration code figure 5 illustrates data output latency from adv# going active for different frequency configuration codes. 4.9.3 data output configuration the output configuration determines how many clocks data will be held valid. the data hold time is configurable as either one or two clocks. the data output configuration must be set to hold data valid for two clock cycles w hen the frequency configuration value 4 and burst length is greater than four words. otherwise, its setting will depend on the system cpus data setup requirement. dq 15-0 (d/q) valid output dq 15-0 (d/q) valid output valid output valid output clk (c) 1 clk data hold 2 clk data hold figure 6. output configuration 4.9.4 wait# configuration the wait# configuration bit controls the behavior of the wait# output signal. this output signal can be set to be asserted during or one clk cycle before an output delay when continuous burst length is enabled. its setting will depend on the system and cpu characteristic. 4.9.5 burst sequence the burst sequence specifies the order in which data is addressed in synchronous burst-mode. this order is programmable as either linear or intel burst order. the continuous burst length only supports linear burst order. the order chosen will depend on the cpu characteristic. see table 8 for more details. 4.9.6 clock configuration the clock configuration configures the device to start a burst cycle, output data, and assert wait# on the rising or falling edge of the clock. clk flexibility helps ease fast boot block flash memory interface to wide range of burst cpus. 4.9.7 burst length the burst length is the number of words that the device will output. the device supports burst lengths of four and eight words. it also supports a continuous burst mode. in continuous burst mode, the device will linearly output data until the internal burst counter reaches the end of the devices burstable address space. bits rcr.2C0 in the read configuration register set the burst length. 4.9.7.1 continuous burst length when operating in the continuous burst mode, the flash memory may incur an output delay when the burst sequence crosses the first sixteen word boundary. the starting address dictates whether or not a delay will occur. if the starting address is aligned to a four word boundary, the delay will not be seen. if the starting address is the end of a four word boundary, the output delay will be equal to the frequency configuration setting; this is the worst case delay. the delay will only take place once during a continuous burst access, and if the burst sequence never crosses a sixteen word boundary, the delay will never happen. using the wait# output pin in the continuous burst configuration, the system is informed if this output delay occurs.
e fast boot block datasheet 21 product preview table 8. sequence and burst length burst addressing sequence (dec) startin g addr. 4 word burst length 8 word burst length continuous burst (dec) linear intel linear intel linear 0 0-1-2-3 0-1-2-3 0-1-2-3- 4-5-6-7 0-1-2-3- 4-5-6-7 0-1-2-3-4-5-6-... 1 1-2-3-0 1-0-3-2 1-2-3-4- 5-6-7-0 1-0-3-2- 5-4-7-6 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-0-1 2-3-4-5- 6-7-0-1 2-3-0-1- 6-7-4-5 2-3-4-5-6-7-8-... 3 3-0-1-2 3-2-1-0 3-4-5-6- 7-0-1-2 3-2-1-0- 7-6-5-4 3-4-5-6-7-8-9-... m m m mm m 6 6-7-0-1- 2-3-4-5 6-7-4-5- 2-3-0-1 6-7-8-9-10-11-12-... 7 7-0-1-2- 3-4-5-6 7-6-5-4- 3-2-1-0 7-8-9-10-11-12-13... m 14 14-15-16-17-18-19-20-... 15 15-16-17-18-19-20-21-... m
fast boot block datasheet e 22 product preview suspend blk. erase loop start write 20h, block address write d0h, block address read status register sr.7 = full status check if desired block erase complete full status check procedure repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last operation to place device in read array mode. sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear staus register command, in cases where multiple blocks are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend block erase 1 0 comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy comments check sr.3 1 = v pp error detect check sr.1 1 = device protect detect wp# = v il read status register data (see above) v pp range error device protect error block erase successful sr.3 = sr.1 = 1 0 1 0 command sequence error sr.4, 5 = 1 0 block erase error sr.5 = 1 0 status register data check sr.4, 5 both 1 = command sequence error check sr.5 1 = block erase error bus operation write write standby read command erase setup erase confirm bus operation standby standby standby standby command figure 7. automated block erase flowchart
e fast boot block datasheet 23 product preview suspend program loop start write 40h, address write data and address read status register sr.7 = full status check if desired program complete full status check procedure repeat for subsequent byte writes. sr full status check can be done after each byte write or after a sequence of program operations. write ffh after the last byte write operation to place device in read array mode. sr.4, sr.3 and sr.1 are only cleared by the clear staus register command, in cases where multiple locations are written before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend program 1 0 comments data = 40h addr = location to be written data = data to be written addr = location to be written check sr.7 1 = wsm ready 0 = wsm busy comments check sr.3 1 = v pp error detect check sr.1 1 = device protect detect wp# = v il read status register data (see above) v pp range error device protect error program successful sr.3 = sr.1 = 1 0 1 0 program error sr.4 = 1 0 status register data check sr.4 1 = data write error bus operation write write standby read command program setup data bus operation standby standby standby command figure 8. automated program flowchart
fast boot block datasheet e 24 product preview start write b0h read status register comments data = b0h addr = x data = d0h addr = x sr.7 = sr.6 = block erase completed write ffh read array data 0 1 0 status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = block erase suspended 0 = block erase completed read or byte write? command erase suspend erase resume bus operation write write read standby standby yes program program loop done write d0h block erase resumed read read array data no 1 figure 9. block erase suspend/resume flowchart
e fast boot block datasheet 25 product preview start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.2 = 1 write ffh read array data program completed done reading yes write ffh write d0h program resumed read array data 0 1 0 read array locations from block other than that being written status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = program suspended 0 = program completed data = d0h addr = x bus operation write write read read standby standby write command program suspend read array program resume figure 10. program suspend/resume flowchart
fast boot block datasheet e 26 product preview 5.0 data protection the fast boot block flash memory architecture features hardware-lockable main blocks and two parameter blocks, so critical c ode can be kept secure while other parameter blocks are programmed or erased as necessary. 5.1 v pp v pplk for complete protection the v pp programming voltage can be held low for complete write protection of all blocks in the flash device. when v pp is below v pplk , any block erase or program operation will result in a error, prompting the corresponding status register bit (sr.3) to be set. 5.2 wp# = v il for block locking the lockable blocks are locked w hen wp# = v il ; any block erase or program operation to a locked block will result in an error, which will be reflected in the status register. for top configuration, the top two parameter and all main blo cks (blocks #37, #38, and #0 through 30 for the 16-mbit, blo cks #21, #22, and #0 through #14 for the 8-mbit) are lockable. for the bottom configuration, the bottom two parameter and all main blo cks (blocks #0, #1, and #8 through #38 for the 16-mbit, blo cks #0, #1, and #8 through #22 for the 8-mbit) are lockable. unlocked blocks can be programmed or erased normally (unless v pp is below v pplk ). 5.3 wp# = v ih for block unlocking wp# controls all block locking and v pp provides protection against spurious writes. table 9 defines the write protection methods. table 9. write protection truth table v pp wp# rst# write protection provided xxv il all blocks locked v il xv ih all blocks locked 3 v pplk v il v ih lockable blocks locked 3 v pplk v ih v ih all blocks unlocked 6.0 v pp voltages intels fast boot block flash memory family provides in-system programming and erase at 2.7 vC3.6 v (3.0 vC3.6 v for automotive temperature) v pp . for customers requiring fast programming in their manufacturing environment, this family of products includes an additional low- cost, high-performance 12 v programming feature. the 12 v v pp mode enhances programming performance during short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 v may be applied to v pp during block erase and program operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. 7.0 power consumption while in operation, the flash device consumes active power. however, intel flash devices have power savings that can significantly reduce overall system power consumption. the automatic power savings (aps) feature reduces power consumption when the device is idle. if ce# is deasserted, the flash enters its standby mode, where current consumption is even lower. the combination of these features minimizes overall memory power and system power consumption. 7.1 active power with ce# at a logic-low level and rst# at a logic- high level, the device is in active mode. active power is the largest contributor to overall system power consumption. minimizing active current has a profound effect on system power consumption, especially for battery-operated devices. 7.2 automatic power savings automatic power savings (aps) provides low- power operation during active mode, allowing the flash to put itself into a low current state when not being accessed. after data is read from the memory array, the devices power consumption enters the aps mode where typical i cc current is comparable to i ccs . the flash stays in this static state with outputs valid until a new location is read.
e fast boot block datasheet 27 product preview 7.3 standby power with ce# at a logic-high level (v ih ) and the cui in read mode, the flash memory is in standby mode, which disables much of the devices circuitry and substantially reduces power consumption. outputs (dq 0 Cdq 15 ) are placed in a high-impedance state independent of the status of the oe# signal. if ce# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. system engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. this will provide a more accurate measure of application-specific power and energy requirements. 7.4 power-up/down operation the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, v pp , v cc , or v ccq , powers-up first. 7.4.1 rst# connection the use of rst# during system reset is important with automated program/erase devices since the system expects to r ead from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting rst# to the system reset si gnal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when v cc voltages are above v lko and v pp is active. since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rst# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 7.4.2 v cc , v pp and rst# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from deep power-down mode or after v cc transitions above v lko (lockout voltage), is read array mode. after any block erase or program operation is complete (even after v pp transitions down to v pplk ), the cui must be reset to read array mode via the read array command if access to the flash memory array is desired. 7.5 power supply decoupling flash memorys power switching characteristics require careful device decoupling. system designers should consider three supply current issues: 1. standby current levels (i ccs ) 2. active current levels (i ccr ) 3. transient peaks produced by falling and rising edges of ce#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 7.5.1 v pp trace on printed circuit boards designing for in-system writes to the flash memory requires special consideration of the v pp power supply trace by the printed circuit board designer. the v pp pin supplies the flash memory cells current for programming and erasing. v pp trace widths and layout should be similar to that of v cc . adequate v pp supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
fast boot block datasheet e 28 product preview 8.0 electrical specifications 8.1 absolute maximum ratings* temperature under bias ............ C40 c to +125 c storage temperature................. C65 c to +125 c voltage on any pin (except v cc , v ccq , and v pp ) C0.5 v to +5.5 v (1) v pp voltage ......................... C0.5 v to +13.5 v (1,2,4) v cc and v ccq voltage ............... C0.2 v to +5.0 v (1) output short circuit current.....................100 ma (3) notice: this datasheet contains preliminary information on products in the design phase of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. *warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. notes: 1. all specified voltages are with respect to gnd. minimum dc voltage is C0.5 v on input/output pins and C0.2 v on v cc and v pp pins. during transitions, this level may undershoot to C2.0 v for periods <20 ns. maximum dc voltage on input/output pins and v cc is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0 v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. v pp program voltage is normally 2.7 vC3.6 v. connection to supply of 11.4 vC12.6 v can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. v pp may be connected to 12 v for a total of 80 hours maximum. 8.2 extended temperature operating conditions symbol parameter notes min max unit t a operating temperature C40 +85 c v cc1 v cc supply voltage 1 2.7 2.85 v v cc2 v cc supply voltage 1 2.7 3.3 v v cc3 v cc supply voltage 1,4 2.7 3.6 v v ccq1 i/o voltage 1,2 1.65 2.5 v v ccq2 i/o voltage 1,2 1.8 2.5 v v ccq3 i/o voltage 1,2,4 2.7 3.6 v v pph1 v pp supply voltage 1 2.7 3.6 v v pph2 v pp supply voltage 1,4 11.4 12.6 v cycling block erase cycling 3 10,000 cycles notes: 1. see dc characteristics tables for voltage range-specific specifications. 2. the voltage swing on the inputs, v in is required to match v ccq . 3. applying v pp = 11.4 v C12.6 v during a program or erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. a hard connection to v pp = 11.4 vC12.6 v is not allowed and can cause damage to the device. 4. v cc , v ccq , and v pp1 must share the same supply when all three are between 2.7 v and 3.6 v.
e fast boot block datasheet 29 product preview 8.3 capacitance (1) t a = +25 c, f = 1 mhz sym parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v note: 1. sampled, not 100% tested. v ccq 0v v ccq /2 v ccq /2 t est p o in ts input output ac test inputs are driven at v ccq min. for a logic "1" and 0.0 v for a logic "0." input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed conditions are when v ccq = 2.7 v. figure 11. transient input/output reference waveform for v cc = 2.7 v - 3.6 v device under test v ccq c l r 2 r 1 out note: see table for component values. figure 12. transient equivalent testing load circuit test configuration component value for worst case speed conditions test configuration c l (pf) r 1 ( w )r 2 ( w ) 2.7 v standard test 50 25k 25k 1.65 v standard test 50 16.7k 16.7k note: c l includes jig capacitance.
fast boot block datasheet e 30 product preview 8.4 dc characteristics extended temperature (1) v cc 2.7 v C3.6 v 2.7 vC2.85 v 2.7 vC3.3 v v ccq 2.7 vC3.6 v 1.65 vC2.5 v 1.65 vC2.5 v sym parameter note typ max typ max typ max unit test conditions i li input load current 6 1 1 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i lo output leakage current 6 10 10 10 a v cc = v cc max v ccq = v ccq max output leakage current for wait# 25 25 25 v in = v ccq or gnd i ccs v cc standby current 6 30 50 20 50 150 250 a v cc = v cc max ce# = rp# = v cc or during program/ erase suspend i ccr v cc read current 4,6 45 60 30 45 40 55 ma asynchronous t avav = min v in = v ih or v il 45 60 30 45 40 55 ma synchronous clk = 33 mhz ce# = v il oe# = v ih burst length = 1 i ccw v cc program current 3,6 8 20 8 20 8 20 ma v pp = v pp1, 2 program in progress i cce v cc erase current 3,6 8 20 8 20 8 20 ma v pp = v pp1 , 2 erase in progress i ppr v pp read current 2 15 2 15 2 15 a v pp v cc 3 50 200 50 200 50 200 a v pp > v cc i ppw v pp program current 3103510351035mav pp =v pp1 program in progress 210210210mav pp = v pp2 program in progress i ppe v pp erase current 3122513251325mav pp = v pp1 program in progress 825825825mav pp = v pp2 program in progress i ppes i ppws v pp erase suspend current 3 50 200 50 200 50 200 a v pp = v pp1 , 2 program or erase suspend in progress
e fast boot block datasheet 31 product preview 8.4 dc characteristics extended temperature (continued) v cc 2.7 v C3.6 v 2.7 vC2.85 v 2.7 vC3.3 v v ccq 2.7 vC3.6 v 1.65 vC2.5 v 1.8 vC2.5 v sym parameter note min max min max min max unit test conditions v il input low voltage C0.4 0.4 C0.2 0.2 C0.2 0.2 v v ih input high voltage v ccq C 0.4v v ccq C 0.2v v ccq C 0.2v v v ol output low voltage 0.10 -0.10 0.10 -0.10 0.10 v v cc = v cc min v ccq = v ccq min i ol = 100 m a v oh output high voltage v ccq C 0.1v v ccq C 0.1v v ccq C 0.1v vv cc = v cc min v ccq = v ccq min i oh = C100 m a v pplk v pp lock-out voltage 2 1.5 1.5 1.5 1.5 v complete write protection v pp1 v pp during 2 2.7 3.6 v v pp2 program and 2 2.7 2.85 v v pp3 erase operations 2 2.7 3.3 v v pp4 2,5 11.4 12.6 11.4 12.6 11.4 12.6 v v lko v cc prog/erase lock voltage 1.5 1.5 1.5 v v lko2 v ccq prog/erase lock voltage 1.2 1.2 1.2 v notes: 1. all currents are in rms unless otherwise noted. typical values at normal v cc , t = +25 c. 2. i cces is specified with device deselected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . 3. erases and program operations are inhibited when v pp v pplk , and not guaranteed outside the valid v pp ranges of v pph1 and v pph2 . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to approximately standby levels, in static operation. 6. applying v pp = 11.4 vC12.6 v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. 7. the specification is the sum of v cc and v ccq currents.
fast boot block datasheet e 32 product preview 8.5 ac characteristics read-only operations (1,6) extended temperature product C95 C120 v cc 3.0 vC3.6 v 2.7 vC3.6 v 2.7 vC3.6 v # sym parameter notes min max min max min max unit r1 t clk clk period 15 15 15 ns r2 t ch (t cl ) clk high (low) time 2.5 2.5 2.5 ns r3 t chcl clk fall (rise) time 5 5 5 ns r4 t avch address valid setup to clk 7 7 7 ns r5 t vlch adv# low setup to clk 7 7 7 ns r6 t elch ce# low setup to clk 7 7 7 ns r7 t chqv clk to output delay 14 16 23 ns r8 t chqx output hold from clk 5 5 5 ns r9 t chax address hold from clk 3 10 10 10 ns r10 t chtl clk to wait# delay 5 13 16 23 ns r11 t avvh address setup to adv# high 10 10 10 ns r12 t elvh ce# low to adv# high 10 10 10 ns r13 t avqv address to output delay 90 95 120 ns r14 t elqv ce# low to output delay 2 90 95 120 ns r15 t vlqv adv# low to output delay 90 95 120 ns r16 t vlvh adv# pulse width low 10 10 10 ns r17 t vhvl adv# pulse width high 4 10 10 10 ns r18 t vhax address hold from adv# high 3 3 3 3 ns r19 t apa page address access time 21 23 30 ns r20 t glqv oe# low to output delay 25 25 30 ns r21 t rhqv rst# high to output delay 600 600 600 ns r22 t ehqz t ghqz ce# or oe# high to output in high z, whichever occurs first 4252525ns r23 t oh output hold from address, ce#, or oe# change, whichever occurs first 4000ns notes: 1. see ac input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed up to t elqv Ct glqv after the falling edge of ce# without impact on t elqv . 3. address hold in synchronous burst-mode is defined as t chax or t vhax , whichever timing specification is satisfied first. 4. sampled, not 100% tested. 5. output loading on wait# equals 15 pf. 6. data bus voltage must be less than or equal to v ccq when a read operation is initiated to guarantee ac specifications.
e fast boot block datasheet 33 product preview r1 r2 r3 clk (c) figure 13. ac waveform for clk input r18 a 19-0 (a) v ih v il valid address r11 r13 r20 r23 dq 15-0 (d/q) rst# (r) r21 v ih v il v oh v ol valid output high z oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r15 r16 adv# (v) v ih v il r17 r12 r14 r22 ce# (e) v ih v il figure 14. ac waveform for single asynchronous read operation from parameter blocks, status register, identifier codes
fast boot block datasheet e 34 product preview r18 r11 r15 r16 r13 r22 a 19-2 (a) a 1-0 (a) adv# (v) ce# (e) v ih v il v ih v il v ih v il v ih v il valid address valid address valid address valid address valid address r14 oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r20 r19 r23 dq 15-0 (d/q) rst# (r) r21 v ih v il v oh v ol valid output valid output valid output valid output high z r17 figure 15. ac waveform for asynchronous page-mode read operations from main blocks
e fast boot block datasheet 35 product preview v ih v il clk (c) note 1 a 19-0 (a) v ih v il valid address r4 r18 r11 r9 r12 r16 r22 adv# (v) ce# (e) v ih v il v ih v il r6 r5 oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r20 r7 r23 dq 15-0 (d/q) v oh v ol valid output high z r17 note: 1. depending upon the frequency configuration code value in the read configuration register, insert clock cycles: frequency configuration 2 insert two clock cycles frequency configuration 3 insert three clock cycles frequency configuration 4 insert four clock cycles frequency configuration 5 insert five clock cycles frequency configuration 6 insert six clock cycles see section 4.9.2 for further information about the frequency configuration and its effect on the initial read. figure 16. ac waveform for single synchronous read operations from parameter blocks, status register, identifier codes
fast boot block datasheet e 36 product preview v ih v il clk (c) note 1 a 19-0 (a) v ih v il valid address r4 r18 r11 r9 r12 r16 r22 adv# (v) ce# (e) v ih v il v ih v il r6 r5 oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r20 r7 r8 r23 dq 15-0 (d/q) v oh v ol valid output valid output valid output valid output high z r17 note: 1. depending upon the frequency configuration code value in the read configuration register, insert clock cycles: frequency configuration 2 insert two clock cycles frequency configuration 3 insert three clock cycles frequency configuration 4 insert four clock cycles frequency configuration 5 insert five clock cycles frequency configuration 6 insert six clock cycles see section 4.9.2 for further information about the frequency configuration and its effect on the initial read. figure 17. ac waveform for synchronous burst read operations, four word burst length, from main blocks
e fast boot block datasheet 37 product preview v ih v il clk (c) note 1 a 19-0 (a) adv# (v) ce# (e) oe# (g) we# (w) v ih v il v ih v il v ih v il v ih v il v ih v il wait# (t) v oh v ol dq 15-0 (d/q) v oh v ol valid output valid output valid output high z valid output valid output r7 r10 r10 note 2 note: 1. this delay will only occur when burst length is configured as continuous. see section 4.9.7 for further information about the behavior of wait#. 2. wait# is configurable. it can be set to assert during or one clk cycle before an output delay. see section 4.9.4 for further information. figure 18. ac waveform for continuous burst read, showing an output delay with data output configuration set to one clock v ih v il clk (c) note 1 a 19-0 (a) adv# (v) ce# (e) oe# (g) we# (w) v ih v il v ih v il v ih v il v ih v il v ih v il wait# (t) v oh v ol dq 15-0 (d/q) v oh v ol valid output high z valid output r7 r10 note 2 r10 note: 1. this delay will only occur when burst length is configured as continuous. see section 4.9.7 for further information about the behavior of wait#. 2. wait# is configurable. it can be set to assert during or one clk cycle before an output delay. see section 4.9.4 for further information. figure 19. ac waveform for continuous burst read, showing an output delay with data output configuration set to one clock
fast boot block datasheet e 38 product preview 8.6 ac characteristics write operations (1, 2) extended temperature valid for all speed and voltage combinations # sym parameter notes min max unit w1 t phwl (t phel ) rst# high recovery to we# (ce#) going low 3 600 s w2 t elwl (t wlel ) ce# (we#) setup to we# (ce#) going low 6 0 ns w3 t wp write pulse width 6 75 ns w4 t vlvh adv# pulse width 10 ns w5 t dvwh (t dveh ) data setup to we# (ce#) going high 4 70 ns w6 t avwh (t aveh ) address setup to we# (ce#) going high 4 75 ns w7 t vleh (t vlwh ) adv# setup to we# (ce#) going high 75 ns w8 t avvh address setup to adv# going high 10 ns w9 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 ns w10 t whdx (t ehdx ) data hold from we# (ce#) high 0 ns w11 t whax (t ehax ) address hold from we# (ce#) high 0 ns w12 t vhax address hold from adv# going high 3 ns w13 t wph write pulse width high 7 20 ns w14 t phwh (t phheh ) wp# setup to we# (ce#) going high 3 200 ns w15 t vpwh (t vpeh )v pp setup to we# (ce#) going high 3 200 ns w16 t whgl (t ehgl ) write recovery before read 0 ns w17 t qvbh wp# hold from valid srd 3,5 0 ns w18 t qvvl v pp hold from valid srd 3,5 0 ns notes: 1. read timing characteristics during block erase and program operations are the same as during read-only operations. refer to ac characteristics read-only operations . 2. a write operation can be initiated and terminated with either ce# or we#. 3. sampled, not 100% tested. 4. refer to table 3 for valid a in and d in for block erase or program. 5. v pp should be held at v pph1/2 until determination of block erase or program success. 6. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . 7. write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). hence, t wph = t whwl = t ehel = t whel = t ehwl .
e fast boot block datasheet 39 product preview valid address valid address w6 w11 w12 w3 w5 w10 w9 w2 w1 w13 data in data in valid srd w4 w7 w8 w16 a 20-0 (a) v ih v il adv# (v) v ih v il ce# (we#) [e(w)] v ih v il oe# [g] v ih v il we# (ce#) [w(e)] v ih v il data [d/q] v ih v il note 6 note 6 note 1 note 2 note 3 note 4 note 5 rst# [p] v ih v il w15 w18 v pp [v] v pph1/2 v pplk v il wp# [b] v ih v il w14 w17 w19 notes: 1. v cc power-up and standby. 2. write block erase or program setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. for read operations, oe# and ce# must be driven active, and we# de-asserted. figure 20. ac waveform for write operations
fast boot block datasheet e 40 product preview 8.7 ac characteristics reset operationextended temperature (a) reset while device is in read mode rst# (r) v ih v il p1 r20 rst# (r) v ih v il p1 p2 r20 rst# (r) v ih v il p1 p2 r20 (b) reset during program or block erase, p1 p2 (c) reset during program or block erase, p1 3 p2 abort complete abort complete figure 21. ac waveform for reset operation table 10. reset specifications # symbol parameter notes min max unit p1 t plph rst# low to reset during read (if rst# is tied to v cc , this specification is not applicable) 2,4 100 ns p2 t plrh rst# low to reset during block erase or program 3,4 22 s notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if t plph is < 100 ns the device may still reset but this is not guaranteed. 3. if rst# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. sampled, but not 100% tested.
e fast boot block datasheet 41 product preview 8.8 extended temperature block erase and program performance (3, 4, 5) 2.7 v v pp 12 v v pp # sym parameter notes typ (1) max typ (1) max unit w19 t whrh1 , program time 2 23.5 200 8 185 s t ehrh1 block program time (parameter) 2 0.10 0.30 0.03 0.10 sec block program time (main) 2 0.8 2.4 0.24 0.8 sec t whrh2 , block erase time (parameter) 2 1 4 0.8 4 sec t ehrh2 block erase time (main) 2 1.8 5 1.1 5 sec t whrh5 , t ehrh5 program suspend latency 6 10 5 10 s t whrh6 , t ehrh6 erase suspend time 13 20 10 12 s notes: 1. typical values measured at t a = +25 c and nominal voltages. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, but not 100% tested. 5. reference the ac waveform for write operations figure 20. 8.9 automotive temperature operating conditions except for the specifications given in this section, all dc and ac characteristics are identical to those listed in the extended temperature specifications. see section 7.2 for extended temperature specifications. symbol parameter notes min max unit t a operating temperature -40 +125 c v cc1 v cc supply voltage 1 3.0 3.6 v v ccq1 i/o voltage 1,2 3.0 3.6 v v pph1 v pp supply voltage 1 3.0 3.6 v v pph2 v pp supply voltage 1,3 11.4 12.6 v cycling parameter block erase cycling 30,000 cycles main block erase cycling 1,000 cycles notes: 1. see dc characteristics tables for voltage range-specific specifications. 2. the voltage swing on the inputs, v in is required to match v ccq . 3. applying v pp = 11.4 v C12.6 v during a program/erase can only be done for a maximum of 1000 cycles on the main and parameter blocks. a hard connection to v pp = 11.4 vC12.6 v is not allowed and can cause damage to the device.
fast boot block datasheet e 42 product preview 8.10 capacitance (1) t a = +25c, f = 1 mhz sym parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v note: 1. sampled, not 100% tested. v ccq 0v v ccq /2 v ccq /2 t est p o in ts input output ac test inputs are driven at 3.0 v for a logic "1" and 0.0 v for a logic "0." input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed conditions are when v ccq = 3.0 v. figure 22. transient input/output reference waveform for v cc = 3.3 v 0.3 v device under test v ccq c l r 2 r 1 out note: see table for component values. figure 23. transient equivalent testing load circuit test configuration component value for worst case speed conditions test configuration c l (pf) r 1 ( w )r 2 ( w ) 3 v standard test 80 25k 25k note: c l includes jig capacitance.
e fast boot block datasheet 43 product preview 8.11 dc characteristics (1) automotive temperature sym parameter note typ max unit test condition i ccs v cc standby current 2,6 40 60 a v cc = v cc max v ccq = v ccq max ce# = rst# = v ih i ccr v cc read current 4,6 60 75 ma asynchronous t avav = min v cc = v cc max v ccq = v ccq max v in = v ih or v il 60 75 ma synchronous clk = 22 mhz ce# = v il oe# = v ih burst length = 1 i ccw v cc program current 3,5,7 8 20 ma v pp = v pph1 (3.0 vC3.6 v) program in progress 820mav pp = v pph2 (11.4 vC12.6 v) program in progress i cce v cc block erase current 3,5,7 8 20 ma v pp = v pph1 (3.0 vC3.6 v) block erase in progress 820mav pp = v pph2 (11.4 vC12.6 v) block erase in progress i ppw v pp program current 3,5,7 15 40 ma v pp = v pph1 (3.0 vC3.6 v) program in progress 10 25 ma v pp = v pph2 (11.4 vC12.6 v) program in progress i ppe v pp block erase current 3,5,7 13 25 ma v pp = v pph1 (3.0 vC3.6 v) block erase in progress 825mav pp = v pph2 (11.4 vC12.6 v) block erase in progress notes: 1. all currents are in rms unless otherwise noted. typical values at normal v cc , t = +25 c. 2. erases and program operations are inhibited when v pp v pplk , and not guaranteed outside the valid v pp ranges of v pph1 and v pph2 . 3. sampled, not 100% tested. 4. automatic power savings (aps) reduces i ccr to approximately standby levels, in static operation. 5. 12 v (11.4 vC12.6 v) can only be applied to v pp for a maximum of 80 hours over the lifetime of the device. v pp should not be permanently tied to 12 v. 6. the specification is the sum of v cc and v ccq currents.
fast boot block datasheet e 44 product preview 8.12 ac characteristics read-only operations (1) automotive temperature # sym parameter notes min max unit r1 t clk clk period 15 ns r2 t ch (t cl ) clk high (low) time 2.5 ns r3 t chcl (t clch ) clk fall (rise) time 5 ns r4 t avch address valid setup to clk 17 ns r5 t vlch adv# low setup to clk 17 ns r6 t elch ce# low setup to clk 17 ns r7 t chqv clk to output delay 30 ns r8 t chqx output hold from clk 5 ns r9 t chax address hold from clk 3 10 ns r10 t chtl (t chth ) clk to wait# delay 5 30 ns r11 t avvh address setup to adv# going high 19 ns r12 t elvh ce# low to adv# going high 19 ns r13 t avqv address to output delay 150 ns r14 t elqv ce# low to output delay 2 150 ns r15 t vlqv adv# low to output delay 150 ns r16 t vlvh adv# pulse width 19 ns r17 t vhvl adv# pulse width 19 ns r18 t vhax address hold from adv# going high 3 3 ns r19 t apa page address access time 35 ns r20 t glqv oe# low to output delay 50 ns r21 t rhqv rst# high to output delay 600 ns r22 t ehqz t ghqz ce# or oe# high to output in high z, whichever occurs first 440ns r23 t oh output hold from address, ce#, or oe# change, whichever occurs first 40 ns notes: 1. see ac input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. 4. output loading on wait# equals 15 pf.
e fast boot block datasheet 45 product preview 8.13 automotive temperature frequency configuration settings table 11. frequency configuration settings for automotive temperature components frequency configuration code input clk frequency 1 reserved 2 22 mhz 3 33 mhz 4 40 mhz 5 50 mhz 6 66 mhz 8.14 automotive temperature block erase and program performance (3,4,5) 3.3 v v pp 12 v v pp # sym parameter notes typ (1) max typ (1) max unit w19 t whrh1 , program time 2 23.5 tdb 8 tdb s t ehrh1 block program time (parameter) 2 0.10 tdb 0.03 tdb sec block program time (main) 2 0.8 tdb 0.24 tdb sec t whrh2 , block erase time (parameter) 2 1 tdb 0.8 tdb sec t ehrh2 block erase time (main) 2 1.8 tdb 1.1 tdb sec t whrh5 , t ehrh5 program suspend latency 6 tdb 5 tdb s t whrh6 , t ehrh6 erase suspend time 13 tdb 10 tdb s notes: 1. typical values measured at t a = +25c and nominal voltages. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, but not 100% tested. 5. reference the ac waveform for write operations figure 20.
fast boot block datasheet e 46 product preview 9.0 ordering information d t 2 8 f 1 6 0 f 3 t 1 2 0 package dt = extended temp., 56-lead ssop de = automotive temp., 56-lead ssop gt = extended temp., 56-ball bga* csp product line designator for all intel flash products access speed (ns) (95,120,150) product family f3 = fast boot block v cc = 2.7v - 3.6v v pp = 2.7v - 3.6v or 11.4v - 12.6v device density 160 = x16 (16-mbit) 800 = x16 (8-mbit) t = top blocking b = bottom blocking valid combinations 56-lead ssop 56-ball m bga csp (1) extended 16m dt28f160f3t120 gt28f160f3t120 dt28f160f3b120 gt28f160f3b120 dt28f160f3t95 gt28f160f3t95 dt28f160f3b95 gt28f160f3b95 extended 8m dt28f800f3t120 gt28f800f3t120 dt28f800f3b120 gt28f800f3b120 dt28f800f3t95 gt28f800f3t95 dt28f800f3b95 gt28f800f3b95 automotive 8 m de28f800b3t150 de28f800b3b150 note: 1. the 56-ball bga package top side mark reads f160f3 [or f800f3]. all product shipping boxes or trays provide the correct information regarding bus architecture.
e fast boot block datasheet 47 product preview 10.0 additional information (1,2) order number document/tool 210830 flash memory databook 292213 ap-655 fast boot block design guide contact intel/distribution sales office fast boot block cpu design guide 297846 comprehensive users guide for m bga* package see intels world wide web home page micro ball grid array package mechanical specification and media information notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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